Due to rapid development of electronic industry, electronic products tend to be light, slim, short, small, integrative, and multi-functional. In order to satisfy the packaging requirement of integration and miniaturization of a semiconductor package, the package type of a semiconductor chip is gradually changed from a single chip type of ball grid array (BGA) or flip chip (FC) to 3D and modular package, therefore, different package structures are developed such as System in Package (SiP), System Integrated Package (SIP) and System in Board (SiB).
However, 3D and modular package provide flip chip (FC) or wire boding, which connect single semiconductor element one by one to a surface of the substrate, or adhere the elements to the surface by applying surface mounting technology (SMT). All the elements are distributed over a surface of a substrate, thus, no benefit is gained from modularization to enhance miniaturization and performance.
Therefore, a method of embedding a semiconductor element in a high density circuit board is proposed. FIG. 1 illustrates a conventional package structure of embedding a semiconductor element in the circuit board. Referring to a cross-sectional view, the package structure comprises a carrier board 10, and at least one cavity 100a is formed on a surface 100 of the carrier board 10; at least one semiconductor chip 11, and a plurality of electrode pads 110 is formed in the semiconductor chip 11, such pads are located on the carrier board 10 as well as embedded in the cavity 100a; a circuit build-up structure 12 is formed on the carrier board 10, and circuit build-up structure 12 is electrically connected to the electrode pads 110 in the semiconductor chip 11 by a plurality of conductive vias 120.
Although the forgoing problem can be solved, embedding a semiconductor chip in a circuit board exists several drawbacks due to the precision of a semiconductor chip integrated with a circuit board and errors of a router machine are uncontrollable while the semiconductor chip is embedded in the circuit board.
Firstly, when performing a build-up process on a semiconductor chip integrated with a circuit board, errors of a router machine and errors occurred in a subsequent fabrication process which limits the precision of electrode pads on the semiconductor chip should be considered. Therefore, after performing the build-up process, inaccurate alignment will be resulted, such that the build-up circuit cannot be effectively aligned to the electrode pad of the chip.
Furthermore, if a build-up process is directly performed without effectively stabilizing a semiconductor chip, the alignment of the semiconductor chip to the circuit board needs to be examined after the build-up process, so as to reduce efficiency, and increase an unknown problem as well as the product cost.